1. Field of the Invention
The present invention generally relates to voltage regulator modules (VRMs) particularly for high-current, low-voltage applications such as the powering of microprocessors and, more particularly, to VRMs of adaptive voltage position (AVP) design.
2. Description of the Prior Art
The design of semiconductor integrated circuits and digital logic circuits, including memories, gate arrays and microprocessors, in particular has long exhibited a trend toward smaller circuit element size and increased density of circuit element integration on a chip in view of increased manufacturing efficiency and improved functionality and performance, particularly in terms of clock speed/cycle time and noise immunity, of the integrated circuit chips which can be realized thereby. However, small circuit element size and limitations on power dissipation requirements (particularly at higher clock speeds (e.g. above 1 GHz), as well as breakdown resistance, has led to designs operating at lower voltages while the number of circuit elements integrated on a single chip has led to requirements for higher currents to power such chips. Currently, typical power supply voltages are about 1.3 volts and can be expected to decrease in future designs. It follows that the allowable difference between maximum and minimum input supply voltages has also greatly diminished with recent designs and may be expected to decrease further. As an example, CPU supply voltage tolerance for a Pentium IV™ processor is only about 130 mV overall (e.g. a voltage variation between 1.28 volts at no load and 1.18 volts at full load .+−.20 millivolts as illustrated in FIG. 4) while corresponding current requirements currently exceed 70 A and can be expected to increase in future designs.
The large power supply current required not only poses demanding challenges in terms of power supply efficiency but also places a heavy burden on management of transient response within such a small input voltage tolerance due to the possibilities of large current steps and very fast current slew rate (e.g. typically 70 A/μsec at the current time and likely to increase in future designs). Thus, particularly for microprocessors and the like, the voltage regulator module (VRM) of a power supply must maintain a low voltage within a tight tolerance range during large current step transients with high slew rate.
To meet such transient requirements, large valued capacitors or numerous capacitors having a large aggregate capacitance in multi-stage filters have been used in the VRM output although such capacitors increase size, weight and cost. It has also been the practice to use feedback arrangements to maintain the VRM output voltage constant, or nearly so, over the entire load range. In such arrangements, the VRM output voltage was typically centered in the output voltage tolerance window and thus the transient voltage spikes must be held to less than one-half of the voltage tolerance window of the powered circuit(s). On the other hand, if overshoot and ringing can be reasonably well-controlled, the VRM output can be held just below the maximum of the voltage tolerance window at light loads and just above the minimum of the voltage tolerance window at full load, substantially the whole voltage tolerance range may be used for the voltage change during the transient and is the basic concept underlying so-called adaptive voltage positioning (AVP). Typical transient conditions of non-AVP and AVP circuits are contrasted in FIG. 1. It is clear that AVP designs allow fewer and/or smaller valued output capacitors to be used at the VRM output. Perhaps more importantly, however, AVP provides near minimum voltage at maximum load which greatly facilitates thermal design of both the VRM and the circuit(s) powered thereby.
The basic concept of AVP is related to the steady state operation of a VRM. That is, ideally, if the transients between steady state full load and minimum load conditions have no spikes, overshoot or ringing (or other oscillations), the entire voltage tolerance window can be utilized to accommodate load transients, as shown in FIG. 2, and the AVP approach is optimal. Moreover, the comparison between the current and output voltage waveforms shown in FIG. 2 indicates that the VRM including AVP is the equivalent of an ideal voltage source and an ideal series resistance Ro, as illustrated in the equivalent circuit also included in FIG. 2.
Thus, in accordance with this concept, a VRM performing as an ideal voltage source with a series resistance (referred to as a “droop resistor”) can achieve AVP easily. However, at low voltage and high current, the power dissipation of the droop resistor is so significant that such a simple approach is not feasible for present and future VRMs. For example, for a 100 Ampere full load current and a 1 mOhm droop resistor (corresponding to a 0.1 V voltage tolerance window), the power loss from the droop resistor alone would be 10 Watts or about 7% to 10% efficiency loss (depending on the supply output voltage near 1V) attributable to the droop resistor of the VRM, alone, while VRMs of other current designs have an overall efficiency in the range of about 86% to 92%.
In order to avoid such a large loss of efficiency while achieving some of the benefits of simplified thermal design alluded to above, an active droop concept of VRM design has been proposed and is in widespread use at the present time in commercially available VRMs. However, all such designs need to sense load current using either MOSFET Rdson (using the synchronous rectifier MOSFET biased for conduction as a low valued resistor) or an inductor DCR sensing scheme (in which the wiring resistance of the inductor is used as a low-valued sensing resistor). Both of these sensing components have a large parameter tolerance (e.g. ±20%) and are subject to pick up of electrical noise. Consequently, it is difficult to achieve regulation within a smaller tolerance window of ±10% or less, such as the load line for the Pentium IV™ processor alluded to above. Further, the power consumed by the active feedback circuit in such arrangements also compromises and limits ultimate efficiency of the VRM, regardless of the active AVP design.